In electronics, logic synthesis is a computerized process by which a description of a circuit's operation, design and organization is automatically converted into a design implementation that comprises logic gates. Common examples of this process involve the synthesis of designs expressed using hardware description languages (HDLs), including very high speed integrated circuit HDL (VHDL) and Verilog, typically at the register transfer level (RTL), that describe a circuit's operation, design and organization. Typically the synthesis tool takes RTL code, a standard cell library and user defined constraints and produces a gate level representation of the design. In producing the representation, it attempts to best meet the user defined constraints. Logic synthesis is one aspect of electronic design automation (EDA).
Logic synthesis systems can be configured to generate specific types of circuits. For example, a conventional synthesis system that is configured to generate random access memory (RAM) arrays, generates an 8-deep latch array (includes 8 latches) as is shown in FIG. 1 based on user defined descriptions. To best meet the user defined descriptions, this conventional synthesis system is programmed to generate the 8-deep latch array using a master flip-flop that feed into N rows of slave latches, followed by an N-to-1 multiplexor arranged as is shown in FIG. 1. The 8-deep latch array shown in FIG. 1 includes a BIST structure (not shown) that can be used to test the array.
Circuit design characteristics that are used to determine the merits of circuit designs that are generated by logic synthesis systems include testability, circuit area, timing and power. These characteristics can depend on the components that are used to implement the designs. Synthesis systems such as those that generate latch arrays such as is shown in FIG. 1, rely on the use of a master flip-flop and a readout multiplexor for implementation purposes. The use of such components can have negative design consequences. For example, the scale of a design that uses a master flip-flop and an N-to-1 readout multiplexor is limited by the amount of layout area that the master flop and the N-to-1 readout multiplexor occupy. In addition, such designs have timing limitations that are attributable to their use of a flip-flop and an N-to-1 multiplexor. Accordingly, a shortcoming of the latch array designs that are generated by conventional logic synthesis systems is the use of a flip-flop and a readout multiplexor in their implementation.